Michael May's blog
It's been awhile since I've posted but over the last few weeks I have studied over the 802.11ad standard and its particulars, along with a detailed review of the wlan flow within ns-3, and I have started on adding a couple of 802.11ad PHY into ns-3.
I have a reasonable grasp of 802.11ad but there are of course a few things I'll need to properly cover when the time comes such as the association beamforming training and medium contention within the announcement period. This stuff will come when I need to add it into ns-3.
I have begun my additions to ns-3 by starting with the channel and PHY layers with the addition of 2 out of 32 different modulation and coding scheme types, the Control PHY at 27 Mbps and a single carrier BPSK PHY at just over a Gbps. I am currently working on the addition of a TxVector object to be passed up and down the stack to allow easy attribute additions in the future.
Over the last couple of weeks I have been writing sections in my background chapter on ns-3 and 802.11. I have detailed how ns-3 works, the objects involved and an overview of how the WiFi model works and is used. With 802.11 I have talked about details of the PHY and MAC layers.
In the next week I will be reviewing the material on 802.11ad.
This week I have been reviewing a lot of material on 802.11 and the wifi model in ns-3 at a higher layer. I have captured traces of simulated and real 802.11 networks and have been analysing these. I am also comparing parts of these traces with relevant documentation to gain an understanding of how it all works. The next part of my work will be writing a number of pages on these reviewed topics to go into the thesis.
This week I began my Masters under the supervision of Dr. Dean Armstrong at Virscient Limited and Dr. Richard Nelson. The purpose of my thesis is to develop a framework of simulation for IEEE 802.11ad using ns-3. 802.11ad is a new wireless standard for multi-Gbps throughput in the 60GHz spectrum. I will be extending ns-3 to support the new MAC and model physical and logical characteristics as well as designing a set of use cases for testing and showcasing the standard.
I have so far been reviewing material on ns-3 as well as learning a bit of Python and C++.
Build an tested a couple of my second revision nodes and they work. Have also been investigating power consumption minimisation and fixing a atomicity issue with the wireless transceiver.
Been flatout over the past couple of weeks working on assignments and my report. Just got another chapter to write and plenty of proof reading and additions to go. Haven't had any time to finish building the boards up and probably wont before the report is due.
This week has just been a mix assignments and a test, although I have made progress of my report with nearly two chapters complete. The new boards have arrived so now it's just a matter of finding time for me to assemble them.
Not a whole lot has happened this week, I have mainly been working on assignments and studying. I have been learning a bit of Latex and I have transferred half of my interim report over but I need to spend more time working on it. Second board has been sent off to be made and components have been ordered so hopefully everything will have arrived by the end of next week.
I have come to the conclusion that the microcontroller I have chosen is not really the best option due to the expense, size and most importantly very low stock availability. So the revision 2 board has been redesigned around a MSP430F5529, this a 80pin QFP with only 8Kb RAM, half the other one, but has enormous stock, is cheaper, and has all the same functionality except for the DACs. The smaller package means I do not have to have a major component on the bottom as I wasn't sure the radio was best suited for underneath. I have also manage to bring out more pins from the micro to a header, along with the JTAG pins. On the antenna front I found a datasheet no longer hosted by the manufacturer for the chip antenna that mentioned the gain, -8.6dBi, which is terrible. Therefore I am doing away with the chip antenna and moving to a SMA connector. This frees up more space and gives the option of using a wire just like the Skatterweb nodes. The board is complete but is being revised now and should be order sometime this week.
Finished boards have been received from assembly and everything checks out, no problems have been detected so far. The boards have been gradually brought to life with minor hiccups in the software like forgetting the micro now controls the radio shutdown pin or the I2C address of the accelerometer has changed from prototyping with a different model.
The range has been tested to 130 meters in open space with 434MHz, 14dbm, using GFSK modulation with no manchester encoding, data rate of 2.4kbps and 36KHz deviation. I will try different configurations though.
I am also going to try to use the board as a USB CDC for displaying received data on the computer so the FTDI UART to USB converter is not needed.